Anirban Basu
Electrical Engineering graduate from Jadavpur University, with MSc from University of Nebraska, currently pursuing PhD and working as Research Assistant at University of Illinois, Urbana-Champaign.
| Headline: | Engineer |
| Skills: | Business, C/C++, Electrical Engineering, Engineering, Entrepreneurship, Languages and Platforms, Leadership, System Administration, Unix, Windows |
| Location: | USA |
| Groups: | Idea to Product UIllinois 2009 |
| Interested in: | Consulting opportunities, Finding team mates, Meeting new people, Providing services to startups, Trading services |
| Schools: | University of California System - Santa Barbara, University of Illinois System - Urbana-Champaign, University of Nebraska System - Lincoln |
WORK EXPERIENCE
| Employer: | Intel Corporation, Components Research Hillsboro , Oregon |
| Position: | Graduate Technical Intern, Device and Memory Research |
| Time period: | April 2007 - July 2007 |
| Description: | Simulation and testing of exploratory memory devices using band-to-band tunneling effect in SOI devices. |
| Employer: | University of Illinois at Urbana-Champaign |
| Position: | Teaching Assistant |
| Time period: | August 2006 - October 2006 |
| Description: | Teaching assistant for an advanced graduate level course called “Science and technology of Micro and Nanolithography” (ECE 598 – Prof. K. Jain) which deals with current state-of-the-art and advanced lithographic technologies.
Teaching assistant for a senior/graduate level course called “Principles of Advanced Microelectronic Processing” (ECE 484 – Prof. K. Jain) which deals with fundamentals of microelectronic processing techniques in industry and state-of-the-art technologies. |
| Employer: | Intel Corporation, ATD Chandler, Arizona |
| Position: | Graduate Technical Intern, Si-integration |
| Time period: | April 2006 - July 2006 |
| Description: | Modeling and simulation of stress induced effects on microprocessor performance and electrical characteristics of die-level circuits due to flip-chip packaging, power analysis of circuits under packaging stress for 65-nm technology. |
| Employer: | University of Illinois at Urbana-Champaign |
| Position: | Research Assistant |
| Time period: | May 2004 - September 2008 |
| Description: | Design and fabrication of high performance AlGaN/GaN transistors for high-power, high-speed, low noise RF applications, RF and DC electrical characterization of transistors using network and parameter analyzers, material characterization using analytical techniques like AES, SIMS, AFM, SEM, and investigation of transport properties using electrical and analytical techniques. |
| Employer: | California NanoSystems Institute, University of California at Santa Barbara |
| Position: | Research Fellow |
| Time period: | August 2003 - May 2004 |
| Description: | Investigation of nanoscale effects including electrical and thermal characterizations of nanometer scale CMOS and hybrid-CMOS circuits, integration of carbon nanotubes with existing silicon technologies. |
| Employer: | University of Nebraska at Lincoln |
| Position: | Research Assistant |
| Time period: | July 2001 - July 2003 |
| Description: | High density plasma processing of different semiconductors to study dry etch characteristics, fabrication of nanoscale tunnel diodes by in situ thermal diffusion of arsenic in germanium at high temperatures as a substitute to ion-implantation technique for the first time. |
EDUCATION
| University: | University of California System - Santa Barbara |
| Time period: | 2002 - 2004 |
| Degree: | Research Fellow, California NanoSystems Institute |
| University: | University of Nebraska System - Lincoln |
| Time period: | 2003 |
| Degree: | Electrical engineering, MSc |
| University: | University of Illinois System - Urbana-Champaign |
| Time period: | 2003 - Present |
| Degree: | PhD candidate and Research Assistant |
PUBLICATIONS
| Articles: | J1. Self-Aligned AlGaN/GaN High Electron Mobility Transistors with 0.18 μm gate-length, V. Kumar, A. Basu, D.-H. Kim, and I. Adesida (Electronics Letters).
J2. 0.25 μm Self-Aligned AlGaN/GaN High Electron Mobility Transistors, V. Kumar, D-H. Kim, A.Basu, I. Adesida, IEEE Electron Device Letters 29, no.1, pp.18-20, 2008. J3. A Study of Fluorine Bombardment on the Electrical Properties of AlGaN/GaN Heterostructures, A. Basu, V. Kumar and I. Adesida, Journal of Vacuum Science and Technology B 25(6), pp. 2607-2610, 2007. J4. Mo/Al/Mo/Au ohmic contact scheme for AlxGa1-xN/GaN HEMTs annealed at 500 ºC, A. Basu, F. Mohammed, S. Guo, B. Peres, I. Adesida, Journal of Vacuum Science and Technology B 24(2), pp. L16-L18, 2006. |
| Papers: | C1. Critical roles of CF4 and SiCl4 plasma treatments on AlGaN/GaN transistor performance, A. Basu and I. Adesida, Gaseous Electronics Conference, Oct 13-17, 2008, Dallas, USA.
C2. Effects and Implications of SiCl4 Reactive Ion Etching Plasma Treatment on AlGaN/GaN High Electron Mobility Transistors, A. Basu and I. Adesida, Electronics Materials Conference, June 25-27, 2008, University of California, Santa Barbara, USA. C3. Technology for Non-Recessed Short Gate Length E-Mode AlGaN/GaN High-Electron Mobility Transistors, A. Basu, V. Kumar and I. Adesida, Compound Semiconductor Manufacturing Technology (CS-MANTECH), April 14-17, 2008, Chicago, USA. C4. Mechanism of improved gate leakage characteristics in CF4 plasma treated AlGaN/GaN HEMTs, A. Basu, L. Wang, Benedict Ofuonye, V. Kumar and I. Adesida, Materials Research Symposium, Mar 24-27, 2008, San Francisco, USA. C5. Effects of fluorine bombardment on the electrical characteristics of AlGaN/GaN high electron mobility transistors, A. Basu, V. Kumar and I. Adesida, International Conference on Nitride Semiconductors, September 16-21, 2007, Las Vegas, USA. C6. 0.15 μm Self-Aligned AlGaN/GaN High Electron Mobility Transistors, V. Kumar, D-H. Kim, A.Basu, I. Adesida, International Conference on Nitride Semiconductors, September 16-21, 2007, Las Vegas, USA. C7. A study of post-bombardment effects of electronegative ions on the electrical properties of AlGaN/GaN two dimensional electron gas, A. Basu, V. Kumar and I. Adesida, Electronics Materials Conference, June 20-22, 2007, Notre Dame University, South Bend, USA. C8. Comparative study of Mo/Al/Mo/Au ohmic contacts on GaN-HEMTs for different Mo:Al concentration, A. Basu, F. M. Mohammed, L. Wang, V. Kumar and I. Adesida, Electronics Materials Conference, June 20-22, 2007, Notre Dame University, South Bend, USA. C9. Self-aligned AlGaN/GaN high electron mobility transistors, V. Kumar, D.-H. Kim, A. Basu and I. Adesida, Device Research Conference, June 18-20, 2007, Notre Dame University, South Bend, USA. C10. A Study of Fluorine Bombardment on the Electrical Properties of AlGaN/GaN Heterostructures, A. Basu, V. Kumar and I. Adesida Electron Ion Photon Beam Nanotechnology Conference, May 29-Jun1, 2007, Denver, USA. |
INFORMATION
| Memberships: | 1. Chairman of IEEE-Electron Devices Society, UIUC student chapter (Region 4), 2005 – 2008.
2. Invited member of the Materials Research Society (MRS), 2008 – 2009. 3. Member of the International Electron Devices Society (EDS), 2003 - present. 4. Student member of Institute of Electrical and Electronics Engineers (IEEE), 2000 - present. 5. Invited reviewer, Semiconductor Science and Technology, Journal of Electronic Materials, Journal of Physics D. 6. Invited reviewer, 41st, 42nd, 43rd, 44th Design Automation Conference. |
| Awards: | 1. Boeing Award for Engineering Student of the Year Honorable Mention, 2008.
2. University of Illinois Intel Scholar, Mentor for Undergraduate Research Program, 2007-2008. 3. California NanoSystems Institute Chancellor’s Fellowship, 2003 –2004. 4. Milton E. Mohr Research Fellowship for achievements and excellence in academics and research in electrical engineering, 2002 – 2003. 5. University Graduate Scholarship (UGS) from the University of Cincinnati, 2001. 6. Four-year scholarship from the National University of Singapore and Massachusetts Institute of Technology (MIT) Alliance, 2001. 7. First Class Distinction with Honors in Bachelor of electrical engineering in 2001. 8. Team leader of IEEE - Calcutta section to the national symposium “MELANGE”, Mumbai in 2001. 9. Selected for the Visiting Summer Research Program (VSRP) in high-energy physics at Tata Institute of Fundamental Research (TIFR), Mumbai working in conjunction with FermiLab, Chicago and CERN, Geneva in 2000. 10. Ranked among top 0.25 % in Indian Institute of Technology Entrance Examination (IIT – JEE) in 1997. 11. Certificate of National Talent (examination conducted nationally, NTSE) by the Govt. of India and scholarship from 1995 – 2001 through National Council of Educational Research and Training. 12. Center first in 1995 in the nationwide examination of Achievement-cum-diagnostic test in Mathematics (ADTM) conducted by Center for Pedagogical Studies in Mathematics (CPSM). 13. Multiple medals for top ranks in Scholastic Aptitude Tests for Science Talent (SATST) conducted by All India Science Teachers’ Association (AISTA) and ADTM. |
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Brian Mcguigan
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